The present invention relates to a method and/or architecture for transferring data bus control between multiple devices generally and, more particularly, to a method and/or architecture for out-of-band look-ahead arbitration for transferring data bus control between multiple devices in a queue expanded mode without a clock cycle penalty.
Referring to FIG. 1, a conventional system 10 for implementing multiqueue first-in first-out (FIFO) devices is shown. The system 10 includes a selector section 12, a selector section 14 and a number of memory sections 16a-16n. The memory sections 16a-16n are each implemented as FIFO devices. The conventional system 10 implements each of the FIFOs 16a-16n as an independent physical memory.
The selector section 12 receives data from a write interface and presents the data to one of the memory sections 16a-16n in response to a write select signal WR_SEL. The selector section 12 selects one of the FIFOs 16a-16n based on the signal WR_SEL. The incoming data is then stored into the appropriate FIFO 16a-16n. Similarly, the selector section 14 presents data to a read interface from one of the memory sections 16a-16n in response to a read select signal RD_SEL. The selector section 14 selects one of the FIFOs 16a-16n based on the signal RD_SEL and reads the data from the appropriate FIFO 16a-16n. 
The present invention concerns an apparatus comprising a plurality of storage devices and a scheduler circuit. Each of the plurality of storage devices may be configured to store and present one or more packets of a data stream over one or more first busses operating at a first speed. The scheduler circuit may be configured to determine which of the plurality of storage devices transmits the packets of the data stream. A second bus that may be configured to synchronize the plurality of devices. The second bus may operate at a second speed.
The objects, features and advantages of the present invention include providing a method and/or architecture for out-of-band look-ahead arbitration that may (i) implement an event driven variable stage pipeline system; (ii) operate with a plurality of clocks; (iii) have a minimum block size less than total round-time delay; (iv) implement a system where the devices that can arbitrate in the same order as that of queue address, which may select the devices randomly; (v) be implemented without an external arbiter; (vi) allow proper communication between the devices, where the communication may be a function of the packet size; (vii) change the latency of the packets according to the size of the packet being processed; (viii) handle (a) any packet size and/or (b) back-to-back reads; (ix) be implemented without open-drain pads; and/or (x) be implemented independently of the latency between addressing the queue and retrieving data.